Public-source company profile
Intel Foundry
Logic and HBM integration for AI, HPC and networkingAI/HPC, data center, client and 3D chiplets
Package architecture and warpage compensationEMIB local-silicon-bridge 2.5D multi-die packaging
Provides dense die-to-die links for large AI/HPC multi-die packages without relying on a full-size silicon interposer, changing the area, cost, assembly and thermo-mechanical trade space.
Official website ↗Official materials
Package architecture and warpage compensationFoveros Direct 3D chiplet integration with Cu-to-Cu hybrid bonding
AI/HPC and data-center designs need denser, lower-resistance die-to-die links than microbumps while controlling heat flow, power delivery and mechanical reliability in vertical stacks.
Official website ↗Official materials
Package architecture and warpage compensationWhen Intel EMIB replaces a full-size interposer with local silicon bridges, where can stiffness and CTE discontinuities concentrate warpage or interface stress in a large multi-die package, and how should package- and board-level validation be structured?
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