Your solution map
Underfill voids and post-cure delamination in large multi-die packages
Check BLNKK's understanding of the problem, then review priority paths, candidate solutions and missing conditions.
Your additions stay in this browserThis page contains curated public problem informationYour search text does not appear in URLs or server records
Your solution map
Check the problem definition, then choose which solutions to explore.
3 priority paths11 candidate solutions11 sources
BLNKK's current understanding
Please check the details- Package architecture
- Large multi-die / 2.5D / high-density interconnects; pitch and gap unconfirmed
- Observation
- Underfill voids or post-cure interface delamination; formation timing unknown
- Process stage
- Dispensing, capillary filling, curing, and subsequent temperature testing
- Variables to validate
- Surface condition, dispense location and volume, material flow, and cure conditions
- Missing information
- Material batch, storage history, flow time, acoustic gates, and pre- / post-cure controls
Paths to assess first
Paths serve different purposes and can be combined01
Dispense volume and capillary fillingConfirm flow paths and fill consistency
First02
Underfill materials and cure windowsConfirm flow, shrinkage, and reliability conditions
First03
Nondestructive interface inspectionLocate defects and validate process changes
FirstCurrent candidate solutions
Sample suitability still needs confirmationDispensing processASYMTEK underfill dispensing workflowNordson Electronics Solutions · Can help answer: How can volume and location provide consistent supply?
→Material evaluationLOCTITE ECCOBOND UF 9000AEHenkel · Can help answer: Is the material suitable for this interconnect and flow path?
→Interface inspectionC-SAM microelectronic interface inspectionNordson Test & Inspection · Can help answer: Where are defects, and do they change across curing?
→Next: confirm engineering conditionsUse 3 key conditions to adjust the assessment order, then choose solutions to compare.
Check engineering conditions →