Chiplet PHY Designer 2025 interconnect simulation

Keysight Technologies · Thermo-mechanical simulation and lifetime prediction

Purpose: Before tapeout, die-to-die links need signal-quality and margin evaluation. Chiplet PHY Designer 2025 compares D2D links using PHY and channel models.
Technical approach: System-level PHY–channel–PHY simulation analyzes VTF, BER and crosstalk. The 2025 announcement adds UCIe 2.0, BoW and QDR clocking support.
Scope of use: Targets high-speed chiplet links in advanced 2.5D/3D or laminate packages. Match the interface, PHY/IP version and actual channel model.
Limitations and open questions: These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitations
Modeled compliance is not hardware interoperability certification. Electrical simulation cannot establish bond cracks, interface failure or customer-product production reliability.
What to prepare
BLNKK recommends preparing TX/RX/PHY models, channel S-parameters, data rate, clocks and margin targets. Record versions, crosstalk, power and temperature assumptions.
Confirm with the supplier
Confirm software/licence versions, UCIe/BoW features and PHY-model compatibility. Agree on BER/VTF/clocking criteria and correlation with physical tests.
Public evidence: The January 2025 announcement documents standards support; the product page describes modeling and bundles. Neither establishes physical interoperability certification.

Supporting references

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