CoWoS-R RDL interposer with CTE-buffering layers

TSMC · Package architecture and warpage compensation

Purpose: Large HPC/AI multi-die packages need dense interconnects while managing thermal-expansion mismatch and joint stress between dies, interposers and substrates.
Technical approach: Uses polymer/copper RDL routing; TSMC describes RDL and C4/underfill compliance as buffering SoC-to-substrate mismatch.
Scope of use: For SoC/HBM and multi-die integration, with co-design of layout, power, cooling, substrate and board requirements.
Limitations and open questions: These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitations
This is a foundry packaging service, not a standalone interposer component. Public architecture does not replace project design rules and reliability assessment.
What to prepare
Prepare die/HBM layout, interconnect/bandwidth needs, power, substrate constraints and thermal, warpage and board-reliability targets.
Confirm with the supplier
Confirm design rules, integration specifications, size/material limits, qualification requirements, schedule, capacity and supply arrangements.
Public evidence: TSMC lists a minimum 4 µm RDL routing pitch (2 µm line/space) and CTE buffering; its 2024 report confirms CoWoS-R’s second year of volume production. Routing pitch is not joint pitch, and the architecture does not guarantee warpage performance for every design.

Supporting references

Find the company’s contact details and ask about this solution through its official channels.