AT&S ECP embedded component packaging
AT&S · Package architecture and warpage compensation
- Purpose
- Compare board-level power-component placement and connections as PDN architecture options.
- Technical approach
- Components occupy laser-machined PCB recesses, with connections formed by laser drilling.
- Scope of use
- An adjacent option for board-level power integration, subject to component and stackup design rules.
- Limitations and open questions
These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitationsShorter-path descriptions do not prove chiplet-droop improvement; actual parasitics and transient behavior need evaluation.
What to prepareBLNKK suggests preparing component data, board/package PDNs, stackups, layouts, load waveforms and comparison measurements.
Confirm with the supplierConfirm embedding rules, available interconnect/parasitic models, thermal design and prototype validation.
- Public evidence
- The ECP page documents embedding, laser connections, design guidelines and graphics-card core-supply applications.
Contact the supplier
Find the company’s contact details and ask about this solution through its official channels.
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BLNKK organizes information from public sources. A company profile does not imply a documented solution. Applicability still needs confirmation against your samples and engineering conditions.