FOCoS high-density fan-out chip-on-substrate

ASE · Package architecture and warpage compensation

Purpose: Large AI/HPC multi-die packages need dense interconnects while balancing thickness, electrical performance, warpage and assembly.
Technical approach: A fan-out RDL module integrates dies and is flip-chip mounted onto a BGA substrate, with chip-first, chip-last and bridge routes.
Scope of use: For high-I/O ASIC/HBM and AI/HPC integration; assess each route’s structure and process separately.
Limitations and open questions: These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitations
Published dimensions and simulation results are configuration-specific. Relative warpage claims do not guarantee customer-package results.
What to prepare
BLNKK suggests preparing die layout, I/O/bandwidth, dimensions, RDL/substrate stack-up, lid/cooling and warpage/reliability targets.
Confirm with the supplier
Confirm the available integration route and design rules, material and carrier conditions, package-warpage and reliability validation scope, and co-design or prototype arrangements.
Public evidence: ASE shows route-specific test vehicles. Its 2025 summary of a 2024 EPTC study examines FOCoS-CL RDL/carrier and substrate/lid effects on stress/warpage.

Supporting references

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