TSMC InFO integrated fan-out packaging

TSMC · Package architecture and warpage compensation

Purpose: Fan-out die-shift investigations can prompt an architecture and placement-tolerance review.
Technical approach: InFO integrates interconnects through RDL and through-InFO vias, with distinct PoP and oS structures.
Scope of use: Official scope includes mobile/HPC applications; confirm option, die layout, design rules and project access with TSMC.
Limitations and open questions: These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitations
Does not correct already-shifted die or guarantee yield. Public descriptions are not project design rules; PoP/oS are not interchangeable.
What to prepare
BLNKK suggests layout, positional tolerance, RDL/via needs, molding measurements and validation targets, considering redesign cost.
Confirm with the supplier
Confirm option, design/data interfaces, positional budget and validation, plus program access and supply conditions.
Public evidence: The page distinguishes processor/DRAM InFO-PoP from substrate-based multi-chiplet InFO-oS.

Contact the supplier

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