Die-position metrology and RDL compensation
Establish consistent pre- and post-mold coordinates and panel maps before discussing RDL compensation.
Items to confirm · 01
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Compare each solution's purpose, inputs and limits.
For “Post-mold die shift and RDL misalignment in fan-out packages”, check what each solution can answer before planning validation.
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BLNKK assessment notes
Update engineering conditions →Your next step
Compare purposes and limits now. Confirm key sample conditions before planning validation.
0 solutions selected0 of 3 relevant conditions confirmedNo solutions selected; these notes cover the current engineering problem.
Priority items to confirm · 3
01Complete coordinate maps availableUnconfirmed
Are pre- and post-mold die translations, rotations, and panel-position maps available in the same coordinate system?
Average displacement alone cannot define local compensation. Retain die and panel coordinates.
Update engineering conditions →02Primary curves completeUnconfirmed
Are measured curves available for mold compound, temporary fixation material, and primary structural materials?
Confirm that viscosity / curing and thermomechanical inputs correspond to the actual batch and process at minimum.
Update engineering conditions →03Flow variants can be comparedUnconfirmed
Can this evaluation compare carriers, fixation methods, or die-first / RDL-first flows?
If the flow is frozen, architectural comparison belongs to future research and is not executable in this round.
Update engineering conditions →Relevant assessment paths
Mold-flow and cure analysis
Confirm that material curves and process settings match the actual batch.
Items to confirm · 02
Carrier and packaging-flow comparison
Confirm whether flow architecture can change and define acceptable comparison scope.
Items to confirm · 03
Assessment preparation checklist
Discussion preparation based on the relevant engineering conditions; not mandatory supplier requirements or a record of evidence already available.
- Complete coordinate maps available
- Primary curves complete
- Flow variants can be compared
Check the comparison table above for each solution’s specific inputs and applicability limits.
Questions to discuss
- Does the map retain each die's translation and rotation in consistent pre- and post-mold coordinates?
- Are panel warpage and the exposure focal plane measured separately rather than inferred from die shift?
- Are temporary fixation material, mold compound, and carrier-release steps compared in controlled groups?
- Does compensated RDL overlay validation cover edges, corners, batches, and thermal history?
- Does the model use measured material curves and cross-check die-shift distributions?
Public references · 11
- Fraunhofer IZM · Panel Level Packaging Consortium 2.0 ↗
View source notes and limits
Research includes precision placement, temporary materials, die-shift / warpage factors, and adaptive imaging.
It provides research directions, not compensation accuracy or yield for this panel.
- Moldex3D · 2024 IC Packaging Technology Conference ↗
View source notes and limits
The manufacturer includes die shift, underfill, curing, and structural analysis within IC packaging simulation capabilities.
The event overview does not provide module versions or validation errors.
- imec · A new approach to fan-out wafer-level packaging ↗
View source notes and limits
A mold-first flow may cause die shift; the research flow forms die-to-die interconnects before molding.
This is a wafer test vehicle, not a panel product specification.
- EV Group · LITHOSCALE die-shift-compensating exposure ↗
View source notes and limits
EVG’s product page and January 2024 paper describe alignment/distortion functions and explicitly require external metrology for die-level compensation and rerouting.
Scope and limitations Compensation does not prevent molding shifts or repair existing opens. The described die-shift workflow excludes thermal influences; traceability annotation does not prove corrected overlay. What to prepare BLNKK suggests documenting shift maps, mark quality, RDL layouts/correction rules and resist/process conditions, with post-exposure alignment checks. Confirm with the supplier Confirm metrology/layout interfaces, correction modes, substrate/mark requirements and the resist-specific process window. Discuss thermal deformation separately.
- SCREEN Semiconductor Solutions · DW-3100 die-shift-compensated direct imaging ↗
View source notes and limits
SCREEN's December 3, 2025 release documents compensation and claims 1 µm-or-less resolution from updated optics.
Scope and limitations Resolution is not overlay accuracy or correction range; universal values are not disclosed. Exposure compensation does not reposition dies; verify actual RDL alignment and connectivity. What to prepare BLNKK suggests preparing displacement/rotation maps, substrate distortion, alignment marks, resist stacks and RDL dimension/overlay targets. Confirm with the supplier Confirm formats, metrology/exposure integration, resist windows, correction limits and acceptance methods before representative exposure trials and measurements.
- Onto Innovation · JetStep panel RDL projection lithography ↗
View source notes and limits
The annual report describes panel RDL and this workflow; a dated 2022 official release provides historical order evidence.
Scope and limitations Exposure adjustment does not physically relocate shifted dies. Public sources do not guarantee project overlay or electrical yield; historical orders do not confirm current availability. What to prepare BLNKK suggests preparing die-shift maps, panel topography, resist thickness, overlay tolerance and validation of coordinate conversion and exposed patterns. Confirm with the supplier Confirm available configuration, substrate/resist suitability, position-data interface, compensation approach and sample alignment validation.
- TSMC · TSMC InFO integrated fan-out packaging ↗
View source notes and limits
The page distinguishes processor/DRAM InFO-PoP from substrate-based multi-chiplet InFO-oS.
Scope and limitations Does not correct already-shifted die or guarantee yield. Public descriptions are not project design rules; PoP/oS are not interchangeable. What to prepare BLNKK suggests layout, positional tolerance, RDL/via needs, molding measurements and validation targets, considering redesign cost. Confirm with the supplier Confirm option, design/data interfaces, positional budget and validation, plus program access and supply conditions.
- Koh Young Technology · Meister D die-placement inspection ↗
View source notes and limits
The official body distinguishes D from D+ and describes inspection of visible microcracks, chipping and foreign material.
Scope and limitations Visible surfaces do not establish die positions after molding. Do not transfer D+ reflective-height capability to D. What to prepare BLNKK suggests representative dies and carriers, placement coordinates, reference marks and relevant defect samples. Confirm with the supplier Confirm model-specific height/tilt performance, coordinate export and integration with downstream RDL alignment.
- Onto Innovation · Firefly G5 panel-level packaging inspection and 3D metrology ↗
View source notes and limits
The indexed official page lists these inspection and metrology modes. Direct access to the page and supporting paper was unavailable during this review.
Scope and limitations Public information does not establish full-field warpage measurement through thermal cycling or detection of every internal defect. What to prepare Prepare sample materials, dimensions and surface details, known-defect samples or images, dimensional tolerances and line throughput targets. Confirm with the supplier Ask about sample compatibility, detection and false-call performance, repeatability, configuration and production-data interfaces.
- Deca Technologies · M-Series fan-out with Adaptive Patterning ↗
View source notes and limits
Current pages explain measurement, design during manufacturing and LDI; the ISS 2019 presentation supplies historical alignment/routing examples.
Scope and limitations Compensation depends on contact/routing rules and implementation. Historical layer counts, yield or reliability examples are not family-wide guarantees. What to prepare BLNKK suggests preparing displacement/rotation distributions, contact/routing rules, panel format, measurement data and existing exposure/data workflows. Confirm with the supplier Confirm the M-Series architecture, APDK and allowed variation, measurement/LDI integration and pilot validation; define warpage acceptance separately.
- Powertech Technology Inc. (PTI) · CLIP chip-last panel-level fan-out packaging ↗
View source notes and limits
The current CLIP page states minimum RDL L/S≥2/2µm; the January 2022 investor presentation also describes known-good RDL integration.
Scope and limitations It cannot reposition embedded dies or guarantee elimination of warpage or yield loss. Published capabilities do not qualify every design. What to prepare BLNKK suggests current flow/shift data, die and pin layouts, RDL design, conversion costs and a validation plan. Confirm with the supplier Confirm design rules, known-good RDL criteria, assembly sequence and stack-specific warpage/reliability evidence.
Full assessment recordExpand for all conditions, path rules and original assessment notes.
Current assessment and next steps
Based on reported conditions and public sources. Ready to assess does not establish sample applicability or root cause. Order does not identify the best solution.
Known conditions · 0
Key unknowns · 3
- Are pre- and post-mold die translations, rotations, and panel-position maps available in the same coordinate system?Average displacement alone cannot define local compensation. Retain die and panel coordinates.
- Are measured curves available for mold compound, temporary fixation material, and primary structural materials?Confirm that viscosity / curing and thermomechanical inputs correspond to the actual batch and process at minimum.
- Can this evaluation compare carriers, fixation methods, or die-first / RDL-first flows?If the flow is frozen, architectural comparison belongs to future research and is not executable in this round.
Paths to assess
Die-position metrology and RDL compensation
Establish consistent pre- and post-mold coordinates and panel maps before discussing RDL compensation.
- Are pre- and post-mold die translations, rotations, and panel-position maps available in the same coordinate system?
Conditions that change this path
- Are pre- and post-mold die translations, rotations, and panel-position maps available in the same coordinate system?Supports assessment: Complete coordinate maps available · Unsuitable for now: No registerable data
Mold-flow and cure analysis
Confirm that material curves and process settings match the actual batch.
- Are measured curves available for mold compound, temporary fixation material, and primary structural materials?
Conditions that change this path
- Are measured curves available for mold compound, temporary fixation material, and primary structural materials?Supports assessment: Primary curves complete · Unsuitable for now: Key curves missing
Carrier and packaging-flow comparison
Confirm whether flow architecture can change and define acceptable comparison scope.
- Can this evaluation compare carriers, fixation methods, or die-first / RDL-first flows?
Conditions that change this path
- Can this evaluation compare carriers, fixation methods, or die-first / RDL-first flows?Supports assessment: Flow variants can be compared · Unsuitable for now: Flow frozen for this round
What to do next
No result provided. Clarify key conditions before arranging an assessment.
- Are pre- and post-mold die translations, rotations, and panel-position maps available in the same coordinate system?
What to prepare
- Displacement maps, carriers, and process conditions
- Geometry, material curves, viscosity, and process settings
- Interconnect architecture, cost, and process compatibility
- Wafer-level redistribution processes with usable marks and die-position data, after validating resist, substrate and pattern-conversion workflows.
- Supplier-listed advanced-packaging wafers and square panels; dimensions, resist compatibility and correction windows require confirmation.
- X500 addresses rectangular-panel advanced-packaging lithography and RDL; confirm resist, panel condition and coordinate interfaces for the project.
- Official scope includes mobile/HPC applications; confirm option, die layout, design rules and project access with TSMC.
- Evaluate accessible dies using the actual carrier, spacing, reflective surfaces and coordinate references.
- Targets advanced IC substrates, fan-out panels, interposers and embedded-die substrates; defect coverage depends on the sample. Panel format, alignment marks and die map Post-mold coordinate reference and lithography interface
- For single- and multi-die M-Series fan-out alignment; wafer/panel formats, architecture and layer count depend on the implementation. Die coordinate/rotation map and fiducials AP design rules and RDL landing margins Compatible LDI/data-flow and shift distribution
- CLIP applications include CPU, GPU, FPGA and thermally sensitive devices; actual routing and stack rules depend on the design. Current chip-first flow and measured shift CLIP-compatible die/I-O/RDL rules and assembly sequence Architecture transfer cost and qualification plan
Questions to discuss
- Does the map retain each die's translation and rotation in consistent pre- and post-mold coordinates?
- Are panel warpage and the exposure focal plane measured separately rather than inferred from die shift?
- Are temporary fixation material, mold compound, and carrier-release steps compared in controlled groups?
- Does compensated RDL overlay validation cover edges, corners, batches, and thermal history?
- Does the model use measured material curves and cross-check die-shift distributions?
Public references
Fraunhofer IZM · Panel Level Packaging Consortium 2.0 ↗It provides research directions, not compensation accuracy or yield for this panel.
Moldex3D · 2024 IC Packaging Technology Conference ↗The event overview does not provide module versions or validation errors.
imec · A new approach to fan-out wafer-level packaging ↗This is a wafer test vehicle, not a panel product specification.
Fraunhofer IZM · White Paper on Panel Level Packaging ↗This describes 2016 research scope, not current commercial equipment limits.
EV Group · LITHOSCALE die-shift-compensating exposure ↗Scope and limitations Compensation does not prevent molding shifts or repair existing opens. The described die-shift workflow excludes thermal influences; traceability annotation does not prove corrected overlay. What to prepare BLNKK suggests documenting shift maps, mark quality, RDL layouts/correction rules and resist/process conditions, with post-exposure alignment checks. Confirm with the supplier Confirm metrology/layout interfaces, correction modes, substrate/mark requirements and the resist-specific process window. Discuss thermal deformation separately.
SCREEN Semiconductor Solutions · DW-3100 die-shift-compensated direct imaging ↗Scope and limitations Resolution is not overlay accuracy or correction range; universal values are not disclosed. Exposure compensation does not reposition dies; verify actual RDL alignment and connectivity. What to prepare BLNKK suggests preparing displacement/rotation maps, substrate distortion, alignment marks, resist stacks and RDL dimension/overlay targets. Confirm with the supplier Confirm formats, metrology/exposure integration, resist windows, correction limits and acceptance methods before representative exposure trials and measurements.
Onto Innovation · JetStep panel RDL projection lithography ↗Scope and limitations Exposure adjustment does not physically relocate shifted dies. Public sources do not guarantee project overlay or electrical yield; historical orders do not confirm current availability. What to prepare BLNKK suggests preparing die-shift maps, panel topography, resist thickness, overlay tolerance and validation of coordinate conversion and exposed patterns. Confirm with the supplier Confirm available configuration, substrate/resist suitability, position-data interface, compensation approach and sample alignment validation.
TSMC · TSMC InFO integrated fan-out packaging ↗Scope and limitations Does not correct already-shifted die or guarantee yield. Public descriptions are not project design rules; PoP/oS are not interchangeable. What to prepare BLNKK suggests layout, positional tolerance, RDL/via needs, molding measurements and validation targets, considering redesign cost. Confirm with the supplier Confirm option, design/data interfaces, positional budget and validation, plus program access and supply conditions.
Koh Young Technology · Meister D die-placement inspection ↗Scope and limitations Visible surfaces do not establish die positions after molding. Do not transfer D+ reflective-height capability to D. What to prepare BLNKK suggests representative dies and carriers, placement coordinates, reference marks and relevant defect samples. Confirm with the supplier Confirm model-specific height/tilt performance, coordinate export and integration with downstream RDL alignment.
Onto Innovation · Firefly G5 panel-level packaging inspection and 3D metrology ↗Scope and limitations Public information does not establish full-field warpage measurement through thermal cycling or detection of every internal defect. What to prepare Prepare sample materials, dimensions and surface details, known-defect samples or images, dimensional tolerances and line throughput targets. Confirm with the supplier Ask about sample compatibility, detection and false-call performance, repeatability, configuration and production-data interfaces.
Deca Technologies · M-Series fan-out with Adaptive Patterning ↗Scope and limitations Compensation depends on contact/routing rules and implementation. Historical layer counts, yield or reliability examples are not family-wide guarantees. What to prepare BLNKK suggests preparing displacement/rotation distributions, contact/routing rules, panel format, measurement data and existing exposure/data workflows. Confirm with the supplier Confirm the M-Series architecture, APDK and allowed variation, measurement/LDI integration and pilot validation; define warpage acceptance separately.
Powertech Technology Inc. (PTI) · CLIP chip-last panel-level fan-out packaging ↗Scope and limitations It cannot reposition embedded dies or guarantee elimination of warpage or yield loss. Published capabilities do not qualify every design. What to prepare BLNKK suggests current flow/shift data, die and pin layouts, RDL design, conversion costs and a validation plan. Confirm with the supplier Confirm design rules, known-good RDL criteria, assembly sequence and stack-specific warpage/reliability evidence.