Relative Cu reveal height and coplanarity
Establish a silicon-relative measurement reference first.
Items to confirm · 01
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For “TSV reveal height and backside coplanarity”, check what each solution can answer before planning validation.
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BLNKK assessment notes
Update engineering conditions →Your next step
Compare purposes and limits now. Confirm key sample conditions before planning validation.
0 solutions selected0 of 4 relevant conditions confirmedNo solutions selected; these notes cover the current engineering problem.
Priority items to confirm · 4
01Comparable relative heights and locationsUnconfirmed
Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
Wafer thickness or warpage cannot replace Cu reveal height. Research sensitivity does not establish sample capability.
Update engineering conditions →02Comparable staged measurements availableUnconfirmed
Can identical locations or comparable regions be measured after thinning and after reveal?
Endpoint maps alone cannot separate upstream thickness variation from new reveal-stage height differences.
Update engineering conditions →03Etch and endpoint traceableUnconfirmed
Are reveal-etch uniformity, time, and endpoint records retained?
Equipment claims do not establish reliable endpoints for this wafer. Do not infer etch recipes without traces.
Update engineering conditions →04Targets and surface stacks definedUnconfirmed
Are height references, surface stacks, and acceptable measurement methods defined for downstream metallization / bonding?
Define targets from actual bonding needs rather than research specimen dimensions. Do not assume CMP is suitable.
Update engineering conditions →Relevant assessment paths
Assessment preparation checklist
Discussion preparation based on the relevant engineering conditions; not mandatory supplier requirements or a record of evidence already available.
- Comparable relative heights and locations
- Comparable staged measurements available
- Etch and endpoint traceable
- Targets and surface stacks defined
Check the comparison table above for each solution’s specific inputs and applicability limits.
Questions to discuss
- Does measurement separate local Cu reveal height from full-wafer topography?
- Can thinning, etching, and endpoints be compared by location?
- What are downstream metallization / bonding targets and Cu / liner limits?
Public references · 7
- NIST · TSV Reveal height and bump dimension metrology by the TSOM method ↗
View source notes and limits
Compares TSV Cu reveal height, diameter, sidewall angle, and within- / across-die variation using TSOM, simulation, and optical profiling.
Research structures are not production qualifications. Sensitivity is not arbitrary-sample resolution or a universal height specification.
- KLA / SPTS · SPTS Etch and Deposition Processes for Advanced Packaging ↗
View source notes and limits
Backside blanket silicon etching exposes Cu TSVs; Rapier XE claims tunable uniformity and endpoint capabilities.
Supplier capabilities provide no wafer-specific reveal target, selectivity, or endpoint recipe.
- DISCO · Tech Briefing 2023 ↗
View source notes and limits
The 2.5D flow diagram places interposer thinning before TSV reveal / bump formation.
An investor-presentation flow provides no grinding / CMP recipe and does not prove grinding caused height variation.
- ACM Research · Ultra SFP copper-overburden removal and planarization ↗
View source notes and limits
The product page explains the mechanism and integrated sequence; sample-specific stacks and endpoints remain to be confirmed.
Scope and limitations The SFP name does not guarantee zero stress or eliminate every warpage mechanism. SFP alone cannot replace the full sequence; the titanium example is not universal. What to prepare BLNKK suggests preparing copper thickness/distribution, electrical continuity, barrier materials, wafer support, endpoints, and dishing or residue measurements. Confirm with the supplier Confirm integration responsibilities, chemistry compatibility, endpoint control, and post-process topography and cleanliness validation.
- Applied Materials · Reflexion LK copper/dielectric CMP planarization ↗
View source notes and limits
The product page documents platform capabilities; the IMAPS presentation illustrates CMP/barrier-profile co-optimization.
Scope and limitations Case-study heights and yields are not universal equipment specifications. CMP surface control does not replace cleaning, bonding or electrical qualification. What to prepare BLNKK suggests preparing film stacks, pattern density, incoming profiles, dishing targets and existing slurry/pad choices, with post-polish topography, particle and bonding comparisons. Confirm with the supplier Confirm material recipes, endpoint/profile options, cleaning compatibility and measurement methods before jointly defining sample trials and bonding-surface acceptance.
- Evident · LEXT OLS5500 3D surface topography ↗
View source notes and limits
The named page lists three methods and semiconductor applications, with specified calibration conditions for its accuracy/repeatability guarantee.
Scope and limitations It does not measure buried voids or continuity, and general semiconductor use does not establish every TSV pitch. The stated guarantee requires specified calibration by authorized personnel. What to prepare BLNKK suggests preparing TSV geometry, exposed materials, optical response, target locations and representative samples with reference measurements. Confirm with the supplier Confirm method/lenses, visible sidewalls/bottoms, field of view/stitching, calibration, repeatability on actual surfaces and data export.
- Evonik Operations GmbH · Evonik AERODISP CMP silica dispersions ↗
View source notes and limits
The current page and April 2021 document identify the material/use and typical properties, not a validated TSV formulation.
Scope and limitations Abrasive alone establishes neither copper/dielectric selectivity nor scratch-free planarity. Evonik recommends protection from extreme heat/freezing and use within six months of manufacture. What to prepare BLNKK suggests preparing exposed materials/topography, chemistry, pad, removal and cleaning data. Record batch/manufacture/storage and retain controls, scratch/residue images. Confirm with the supplier Confirm current specifications, particle/aggregate distribution, chemistry/metal compatibility and storage/redispersion/filtration. Agree on actual CMP validation of selectivity, morphology and residues.
Full assessment recordExpand for all conditions, path rules and original assessment notes.
Current assessment and next steps
Based on reported conditions and public sources. Ready to assess does not establish sample applicability or root cause. Order does not identify the best solution.
Known conditions · 0
Key unknowns · 4
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Wafer thickness or warpage cannot replace Cu reveal height. Research sensitivity does not establish sample capability.
- Can identical locations or comparable regions be measured after thinning and after reveal?Endpoint maps alone cannot separate upstream thickness variation from new reveal-stage height differences.
- Are reveal-etch uniformity, time, and endpoint records retained?Equipment claims do not establish reliable endpoints for this wafer. Do not infer etch recipes without traces.
- Are height references, surface stacks, and acceptable measurement methods defined for downstream metallization / bonding?Define targets from actual bonding needs rather than research specimen dimensions. Do not assume CMP is suitable.
Paths to assess
Relative Cu reveal height and coplanarity
Establish a silicon-relative measurement reference first.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
Conditions that change this path
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Supports assessment: Comparable relative heights and locations · Unsuitable for now: Only thickness / warpage
Staged thinning-to-etch windows
Complete staged and endpoint records first.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
- Can identical locations or comparable regions be measured after thinning and after reveal?
- Are reveal-etch uniformity, time, and endpoint records retained?
Conditions that change this path
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Supports assessment: Comparable relative heights and locations · Unsuitable for now: Only thickness / warpage
- Can identical locations or comparable regions be measured after thinning and after reveal?Supports assessment: Comparable staged measurements available · Unsuitable for now: Only final height maps
- Are reveal-etch uniformity, time, and endpoint records retained?Supports assessment: Etch and endpoint traceable · Unsuitable for now: Key traces missing
Pre-bond surface-planarization requirements
Define downstream bonding and surface targets first.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
- Are height references, surface stacks, and acceptable measurement methods defined for downstream metallization / bonding?
Conditions that change this path
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Supports assessment: Comparable relative heights and locations · Unsuitable for now: Only thickness / warpage
- Are height references, surface stacks, and acceptable measurement methods defined for downstream metallization / bonding?Supports assessment: Targets and surface stacks defined · Unsuitable for now: Bonding targets undefined
What to do next
No result provided. Clarify key conditions before arranging an assessment.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
What to prepare
- Representative TSV geometry and optical surfaces; same-location references and reference heights
- Staged height maps; actual silicon / liner / Cu stacks and support; endpoint and uniformity records
- Relative heights and staged maps; downstream bonding targets; traces and surface stacks
- TSV backside silicon removal after checking carrier support, remaining silicon, stop layers and target reveal height.
- ACM lists TSV and FOWLP. Its TSV example proceeds through bulk copper removal, CMP to titanium and titanium wet etch.
- A 300 mm platform; Applied/Besi's 2023 presentation lists TSV planarization, reveal polishing and hybrid-bond copper CMP roles.
- Select optics and methods for the surface response and geometry; verify accessible regions on representative TSV samples.
- Evonik lists CMP/semiconductor polishing; assess actual exposed materials, chemistry, pad and cleaning together.
Questions to discuss
- Does measurement separate local Cu reveal height from full-wafer topography?
- Can thinning, etching, and endpoints be compared by location?
- What are downstream metallization / bonding targets and Cu / liner limits?
Public references
NIST · TSV Reveal height and bump dimension metrology by the TSOM method ↗Research structures are not production qualifications. Sensitivity is not arbitrary-sample resolution or a universal height specification.
KLA / SPTS · SPTS Etch and Deposition Processes for Advanced Packaging ↗Supplier capabilities provide no wafer-specific reveal target, selectivity, or endpoint recipe.
DISCO · Tech Briefing 2023 ↗An investor-presentation flow provides no grinding / CMP recipe and does not prove grinding caused height variation.
NIST · Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via ↗The research uses W TSVs. It cannot define Cu-TSV keep-out distances; it supports retaining a separate silicon-stress decision.
ASE · Failure Analysis Lab ↗Capabilities do not guarantee sample localization or specify mold-sealing recipes.
DISCO · Dry Polishing (Stress Relief) ↗Supplier research provides no wafer crack / debond cause or TSV-reveal planarization recipe.
ACM Research · Ultra SFP copper-overburden removal and planarization ↗Scope and limitations The SFP name does not guarantee zero stress or eliminate every warpage mechanism. SFP alone cannot replace the full sequence; the titanium example is not universal. What to prepare BLNKK suggests preparing copper thickness/distribution, electrical continuity, barrier materials, wafer support, endpoints, and dishing or residue measurements. Confirm with the supplier Confirm integration responsibilities, chemistry compatibility, endpoint control, and post-process topography and cleanliness validation.
Applied Materials · Reflexion LK copper/dielectric CMP planarization ↗Scope and limitations Case-study heights and yields are not universal equipment specifications. CMP surface control does not replace cleaning, bonding or electrical qualification. What to prepare BLNKK suggests preparing film stacks, pattern density, incoming profiles, dishing targets and existing slurry/pad choices, with post-polish topography, particle and bonding comparisons. Confirm with the supplier Confirm material recipes, endpoint/profile options, cleaning compatibility and measurement methods before jointly defining sample trials and bonding-surface acceptance.
Evident · LEXT OLS5500 3D surface topography ↗Scope and limitations It does not measure buried voids or continuity, and general semiconductor use does not establish every TSV pitch. The stated guarantee requires specified calibration by authorized personnel. What to prepare BLNKK suggests preparing TSV geometry, exposed materials, optical response, target locations and representative samples with reference measurements. Confirm with the supplier Confirm method/lenses, visible sidewalls/bottoms, field of view/stitching, calibration, repeatability on actual surfaces and data export.
Evonik Operations GmbH · Evonik AERODISP CMP silica dispersions ↗Scope and limitations Abrasive alone establishes neither copper/dielectric selectivity nor scratch-free planarity. Evonik recommends protection from extreme heat/freezing and use within six months of manufacture. What to prepare BLNKK suggests preparing exposed materials/topography, chemistry, pad, removal and cleaning data. Record batch/manufacture/storage and retain controls, scratch/residue images. Confirm with the supplier Confirm current specifications, particle/aggregate distribution, chemistry/metal compatibility and storage/redispersion/filtration. Agree on actual CMP validation of selectivity, morphology and residues.