Relative Cu reveal height and coplanarity
Conditions unconfirmedEstablish a silicon-relative measurement reference first.
Unconfirmed: Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Engineering conditions
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For “TSV reveal height and backside coplanarity”, add details that may change the assessment order and check the basis and limits of each candidate.
Conditions can change the orderUnknown conditions are never assumed to be satisfiedAll choices stay in this browser
Engineering conditions
Use 4 key conditions to see how the assessment order changes.
Separate relative Cu reveal height from full-wafer topography, then use staged thinning / reveal maps to define upstream, etch, or pre-bond surface requirements. Leave unknowns unconfirmed; “ready to evaluate” means complete method inputs, not diagnosis or qualification.
Confirmed: 0 / 4 conditions0 paths ready for initial assessment
Height evidence
Staged history
Bonding targets
All path assessments
Live assessment
Current assessment order
Staged thinning-to-etch windows
Conditions unconfirmedComplete staged and endpoint records first.
Unconfirmed: Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?; Can identical locations or comparable regions be measured after thinning and after reveal?; Are reveal-etch uniformity, time, and endpoint records retained?Pre-bond surface-planarization requirements
Conditions unconfirmedDefine downstream bonding and surface targets first.
Unconfirmed: Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?; Are height references, surface stacks, and acceptable measurement methods defined for downstream metallization / bonding?candidate solutions
Assessment with your current conditions
TSOM Cu reveal-height research-method evaluationNISTEstablish a silicon-relative measurement reference first.
Conditions unconfirmedRapier XE reveal-uniformity and endpoint approachKLA / SPTSComplete staged and endpoint records first.
Conditions unconfirmedStaged-window and pre-bond planarization-requirement reviewBLNKK engineering review request (provider unconfirmed)Complete staged and endpoint records first.
Conditions unconfirmedSPTS Omega Rapier XE backside TSV reveal etchingKLAComplete staged and endpoint records first.
Conditions unconfirmedUltra SFP copper-overburden removal and planarizationACM ResearchDefine downstream bonding and surface targets first.
Conditions unconfirmedReflexion LK copper/dielectric CMP planarizationApplied MaterialsDefine downstream bonding and surface targets first.
Conditions unconfirmedLEXT OLS5500 3D surface topographyEvidentEstablish a silicon-relative measurement reference first.
Conditions unconfirmedEvonik AERODISP CMP silica dispersionsEvonik Operations GmbHDefine downstream bonding and surface targets first.
Conditions unconfirmedThe order changes only with conditions you confirm. Public information cannot establish suitability for your actual samples.
New test result? Update your assessment
After one round of comparisons, choose the next step based on actual observations.
Results only change the order of the next investigation; they do not modify condition answers, prove a root cause, or qualify a solution.
Current assessment and next steps
Based on reported conditions and public sources. Ready to assess does not establish sample applicability or root cause. Order does not identify the best solution.
Known conditions · 0
Key unknowns · 4
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Wafer thickness or warpage cannot replace Cu reveal height. Research sensitivity does not establish sample capability.
- Can identical locations or comparable regions be measured after thinning and after reveal?Endpoint maps alone cannot separate upstream thickness variation from new reveal-stage height differences.
- Are reveal-etch uniformity, time, and endpoint records retained?Equipment claims do not establish reliable endpoints for this wafer. Do not infer etch recipes without traces.
- Are height references, surface stacks, and acceptable measurement methods defined for downstream metallization / bonding?Define targets from actual bonding needs rather than research specimen dimensions. Do not assume CMP is suitable.
Paths to assess
Relative Cu reveal height and coplanarity
Establish a silicon-relative measurement reference first.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
Conditions that change this path
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Supports assessment: Comparable relative heights and locations · Unsuitable for now: Only thickness / warpage
Staged thinning-to-etch windows
Complete staged and endpoint records first.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
- Can identical locations or comparable regions be measured after thinning and after reveal?
- Are reveal-etch uniformity, time, and endpoint records retained?
Conditions that change this path
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?Supports assessment: Comparable relative heights and locations · Unsuitable for now: Only thickness / warpage
- Can identical locations or comparable regions be measured after thinning and after reveal?Supports assessment: Comparable staged measurements available · Unsuitable for now: Only final height maps
- Are reveal-etch uniformity, time, and endpoint records retained?Supports assessment: Etch and endpoint traceable · Unsuitable for now: Key traces missing
What to do next
No result provided. Clarify key conditions before arranging an assessment.
- Are TSV heights relative to surrounding silicon mapped with fixed sampling locations and references?
What to prepare
- Representative TSV geometry and optical surfaces; same-location references and reference heights
- Staged height maps; actual silicon / liner / Cu stacks and support; endpoint and uniformity records
Questions to discuss
- Does measurement separate local Cu reveal height from full-wafer topography?
- Can thinning, etching, and endpoints be compared by location?
Public references
NIST · TSV Reveal height and bump dimension metrology by the TSOM method ↗Research structures are not production qualifications. Sensitivity is not arbitrary-sample resolution or a universal height specification.
KLA / SPTS · SPTS Etch and Deposition Processes for Advanced Packaging ↗Supplier capabilities provide no wafer-specific reveal target, selectivity, or endpoint recipe.
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Related solutions
8 candidate solutions
Selected: 0 / 3 solutionsAdd any solution below to compare. You can compare up to 3 at a time.
Select at least 2 solutions01
TSOM Cu reveal-height research-method evaluationInstitutional research methodPublic information compiled by BLNKK · Participation and sample applicability to be confirmed
TSOM Cu reveal-height research-method evaluation
NIST
Research demonstrations support relative height / dimensional comparison for engineering measurement-feasibility assessment.
Basis: NIST：TSV Reveal height and bump dimension metrology by the TSOM methodCheck prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueCatalogue entry pending
The reviewed public information describes a workflow. It has not been linked to a specific product in the BLNKK solution catalogue.
- Representative TSV geometry and optical surfaces
- Same-location references and reference heights
- Claiming arbitrary-sample resolution from nanometer sensitivity
- Treating research height ranges as acceptance specifications
Primary sources behind these assessmentsNIST：TSV Reveal height and bump dimension metrology by the TSOM method ↗
02
Rapier XE reveal-uniformity and endpoint approachPublicly documented methods / capabilitiesPublic information compiled by BLNKK · Participation and sample applicability to be confirmed
Rapier XE reveal-uniformity and endpoint approach
KLA / SPTS
Compare public blanket-silicon-etch capabilities with staged traces; confirm sample and stack compatibility first.
Basis: KLA / SPTS：SPTS Etch and Deposition Processes for Advanced Packaging；DISCO：Tech Briefing 2023Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueCatalogue entry pending
The reviewed public information describes a workflow. It has not been linked to a specific product in the BLNKK solution catalogue.
- Staged height maps
- Actual silicon / liner / Cu stacks and support
- Endpoint and uniformity records
- Specifying etch time without traces
- Replacing height validation with capacity / rate claims
Primary sources behind these assessmentsKLA / SPTS：SPTS Etch and Deposition Processes for Advanced Packaging ↗DISCO：Tech Briefing 2023 ↗
03
Staged-window and pre-bond planarization-requirement reviewEditorial research / Service availability to be confirmedPublic information compiled by BLNKK · Participation and sample applicability to be confirmed
Staged-window and pre-bond planarization-requirement review
BLNKK engineering review request (provider unconfirmed)
Staged localization and downstream targets are both needed for comparable planarization requirements.
Basis: NIST：TSV Reveal height and bump dimension metrology by the TSOM method；KLA / SPTS：SPTS Etch and Deposition Processes for Advanced Packaging；DISCO：Tech Briefing 2023NIST：TSV Reveal height and bump dimension metrology by the TSOM method ↗KLA / SPTS：SPTS Etch and Deposition Processes for Advanced Packaging ↗DISCO：Tech Briefing 2023 ↗
Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueCatalogue entry pending
The reviewed public information describes a workflow. It has not been linked to a specific product in the BLNKK solution catalogue.
- Relative heights and staged maps
- Downstream bonding targets
- Traces and surface stacks
- Selecting CMP before targets are defined
- Treating Cu reveal deviations as TSV-fill voids
04
Direct candidatePublicly offered; confirm configuration and availabilityBLNKK public-source review · Applicability unconfirmed
SPTS Omega Rapier XE backside TSV reveal etching
KLA
Distinguish thinning and silicon-etch contributions to nonuniform backside TSV reveal height.
Basis: Page 2 of KLA's April 19, 2022 process brochure identifies Rapier XE for silicon via-reveal etching.Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueSame catalogued solution
KLASPTS Omega Rapier XE backside TSV reveal etchingOpen solution details →- TSV backside silicon removal after checking carrier support, remaining silicon, stop layers and target reveal height.
- Scope and limitations Silicon reveal is not copper etching or a final bond-surface coplanarity guarantee. Other Omega/deposition module capabilities are separate. What to prepare BLNKK suggests pre/post-thinning and etch height maps, edge data, TSV stackup, remaining silicon and carrier conditions. Confirm with the supplier Confirm endpoint, uniformity tuning, stop-layer/carrier compatibility and representative-stack trials, including subsequent planarization needs.
Primary sources behind these assessmentsKLA / SPTS：SPTS Etch and Deposition Processes for Advanced Packaging ↗
05
Supporting analysis or measurementPublicly offered; confirm project configuration and availabilityBLNKK public-source review · Applicability unconfirmed
Ultra SFP copper-overburden removal and planarization
ACM Research
Compare copper-overburden removal and subsequent planarization after TSV fill or fan-out RDL processing.
Basis: The product page explains the mechanism and integrated sequence; sample-specific stacks and endpoints remain to be confirmed.Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueSupporting inspection method
ACM ResearchUltra SFP copper-overburden removal and planarizationOpen solution details →- ACM lists TSV and FOWLP. Its TSV example proceeds through bulk copper removal, CMP to titanium and titanium wet etch.
- Scope and limitations The SFP name does not guarantee zero stress or eliminate every warpage mechanism. SFP alone cannot replace the full sequence; the titanium example is not universal. What to prepare BLNKK suggests preparing copper thickness/distribution, electrical continuity, barrier materials, wafer support, endpoints, and dishing or residue measurements. Confirm with the supplier Confirm integration responsibilities, chemistry compatibility, endpoint control, and post-process topography and cleanliness validation.
Primary sources behind these assessmentsACM Research：Ultra SFP copper-overburden removal and planarization ↗
06
Supporting analysis or measurementPublicly offered; confirm project configuration and availabilityBLNKK public-source review · Applicability unconfirmed
Reflexion LK copper/dielectric CMP planarization
Applied Materials
Assess copper/dielectric height differences in TSV planarization and hybrid-bond surfaces alongside contamination and bonding results.
Basis: The product page documents platform capabilities; the IMAPS presentation illustrates CMP/barrier-profile co-optimization.Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueSupporting inspection method
Applied MaterialsReflexion LK copper/dielectric CMP planarizationOpen solution details →- A 300 mm platform; Applied/Besi's 2023 presentation lists TSV planarization, reveal polishing and hybrid-bond copper CMP roles.
- Scope and limitations Case-study heights and yields are not universal equipment specifications. CMP surface control does not replace cleaning, bonding or electrical qualification. What to prepare BLNKK suggests preparing film stacks, pattern density, incoming profiles, dishing targets and existing slurry/pad choices, with post-polish topography, particle and bonding comparisons. Confirm with the supplier Confirm material recipes, endpoint/profile options, cleaning compatibility and measurement methods before jointly defining sample trials and bonding-surface acceptance.
Primary sources behind these assessmentsApplied Materials：Reflexion LK copper/dielectric CMP planarization ↗
07
Supporting analysis or measurementPublicly offered; confirm configuration and scopeBLNKK public-source review · Applicability unconfirmed
LEXT OLS5500 3D surface topography
Evident
Compare accessible surface heights and local topography after TSV reveal.
Basis: The named page lists three methods and semiconductor applications, with specified calibration conditions for its accuracy/repeatability guarantee.Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueSupporting inspection method
EvidentLEXT OLS5500 3D surface topographyOpen solution details →- Select optics and methods for the surface response and geometry; verify accessible regions on representative TSV samples.
- Scope and limitations It does not measure buried voids or continuity, and general semiconductor use does not establish every TSV pitch. The stated guarantee requires specified calibration by authorized personnel. What to prepare BLNKK suggests preparing TSV geometry, exposed materials, optical response, target locations and representative samples with reference measurements. Confirm with the supplier Confirm method/lenses, visible sidewalls/bottoms, field of view/stitching, calibration, repeatability on actual surfaces and data export.
Primary sources behind these assessmentsEvident：LEXT OLS5500 3D surface topography ↗
08
Supporting analysis or measurementPublicly offered; confirm configuration and availabilityBLNKK public-source review · Applicability unconfirmed
Evonik AERODISP CMP silica dispersions
Evonik Operations GmbH
Assess a CMP abrasive ingredient in TSV-reveal/topography comparisons alongside removal selectivity, scratches and post-cleaning results.
Basis: The current page and April 2021 document identify the material/use and typical properties, not a validated TSV formulation.Check prerequisites, exclusions and catalogue relationships
Relationship to the solution catalogueSupporting inspection method
Evonik Operations GmbHEvonik AERODISP CMP silica dispersionsOpen solution details →- Evonik lists CMP/semiconductor polishing; assess actual exposed materials, chemistry, pad and cleaning together.
- Scope and limitations Abrasive alone establishes neither copper/dielectric selectivity nor scratch-free planarity. Evonik recommends protection from extreme heat/freezing and use within six months of manufacture. What to prepare BLNKK suggests preparing exposed materials/topography, chemistry, pad, removal and cleaning data. Record batch/manufacture/storage and retain controls, scratch/residue images. Confirm with the supplier Confirm current specifications, particle/aggregate distribution, chemistry/metal compatibility and storage/redispersion/filtration. Agree on actual CMP validation of selectivity, morphology and residues.
Primary sources behind these assessmentsEvonik Operations GmbH：Evonik AERODISP CMP silica dispersions ↗
Missing evidence and suitability conditions
- Wafer measurement feasibility, planarization / CMP adoption sources, and bonding acceptance values are missing.
- Supplier participation, sample validation, and actual professional responses are not yet confirmed; public capabilities do not establish willingness to take on the work.
- This local method has not yet been published as a canonical solution that demonstrates the same relationship.
References
10 manufacturer or institutional sources
Expand reviewed sources and limitations
References
10 manufacturer or institutional sources
01
Standards / institutional sourcesTSV Reveal height and bump dimension metrology by the TSOM methodNIST · Reviewed 2026-10-04
↗02Compares TSV Cu reveal height, diameter, sidewall angle, and within- / across-die variation using TSOM, simulation, and optical profiling.
Limit: Research structures are not production qualifications. Sensitivity is not arbitrary-sample resolution or a universal height specification.Manufacturer product informationSPTS Etch and Deposition Processes for Advanced PackagingKLA / SPTS · Reviewed 2026-10-04
↗03Backside blanket silicon etching exposes Cu TSVs; Rapier XE claims tunable uniformity and endpoint capabilities.
Limit: Supplier capabilities provide no wafer-specific reveal target, selectivity, or endpoint recipe.Manufacturer technical informationTech Briefing 2023DISCO · Reviewed 2026-10-04
↗04The 2.5D flow diagram places interposer thinning before TSV reveal / bump formation.
Limit: An investor-presentation flow provides no grinding / CMP recipe and does not prove grinding caused height variation.Standards / institutional sourcesMicro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon viaNIST · Reviewed 2026-10-04
↗05Uses Raman measurements and models to compare distance-dependent silicon stress around TSVs.
Limit: The research uses W TSVs. It cannot define Cu-TSV keep-out distances; it supports retaining a separate silicon-stress decision.Manufacturer product informationFailure Analysis LabASE · Reviewed 2026-10-04
↗06Lists mold delamination / incomplete filling, TSV voids / nonprotrusion, and nondestructive localization before sections / FIB.
Limit: Capabilities do not guarantee sample localization or specify mold-sealing recipes.Manufacturer technical informationDry Polishing (Stress Relief)DISCO · Reviewed 2026-10-04
↗07Discusses post-thinning strength / warpage and stress relief of fine-grinding damage.
Limit: Supplier research provides no wafer crack / debond cause or TSV-reveal planarization recipe.Manufacturer product informationUltra SFP copper-overburden removal and planarizationACM Research · Reviewed 2026-10-06
↗08The product page explains the mechanism and integrated sequence; sample-specific stacks and endpoints remain to be confirmed.
Limit: Scope and limitations The SFP name does not guarantee zero stress or eliminate every warpage mechanism. SFP alone cannot replace the full sequence; the titanium example is not universal. What to prepare BLNKK suggests preparing copper thickness/distribution, electrical continuity, barrier materials, wafer support, endpoints, and dishing or residue measurements. Confirm with the supplier Confirm integration responsibilities, chemistry compatibility, endpoint control, and post-process topography and cleanliness validation.Manufacturer product informationReflexion LK copper/dielectric CMP planarizationApplied Materials · Reviewed 2026-10-06
↗09The product page documents platform capabilities; the IMAPS presentation illustrates CMP/barrier-profile co-optimization.
Limit: Scope and limitations Case-study heights and yields are not universal equipment specifications. CMP surface control does not replace cleaning, bonding or electrical qualification. What to prepare BLNKK suggests preparing film stacks, pattern density, incoming profiles, dishing targets and existing slurry/pad choices, with post-polish topography, particle and bonding comparisons. Confirm with the supplier Confirm material recipes, endpoint/profile options, cleaning compatibility and measurement methods before jointly defining sample trials and bonding-surface acceptance.Manufacturer product informationLEXT OLS5500 3D surface topographyEvident · Reviewed 2026-10-06
↗10The named page lists three methods and semiconductor applications, with specified calibration conditions for its accuracy/repeatability guarantee.
Limit: Scope and limitations It does not measure buried voids or continuity, and general semiconductor use does not establish every TSV pitch. The stated guarantee requires specified calibration by authorized personnel. What to prepare BLNKK suggests preparing TSV geometry, exposed materials, optical response, target locations and representative samples with reference measurements. Confirm with the supplier Confirm method/lenses, visible sidewalls/bottoms, field of view/stitching, calibration, repeatability on actual surfaces and data export.Manufacturer product informationEvonik AERODISP CMP silica dispersionsEvonik Operations GmbH · Reviewed 2026-10-06
↗The current page and April 2021 document identify the material/use and typical properties, not a validated TSV formulation.
Limit: Scope and limitations Abrasive alone establishes neither copper/dielectric selectivity nor scratch-free planarity. Evonik recommends protection from extreme heat/freezing and use within six months of manufacture. What to prepare BLNKK suggests preparing exposed materials/topography, chemistry, pad, removal and cleaning data. Record batch/manufacture/storage and retain controls, scratch/residue images. Confirm with the supplier Confirm current specifications, particle/aggregate distribution, chemistry/metal compatibility and storage/redispersion/filtration. Agree on actual CMP validation of selectivity, morphology and residues.Before assessment
Questions to ask before assessment
Expand assessment checklist
Before assessment
Questions to ask before assessment
- Does measurement separate local Cu reveal height from full-wafer topography?
- Can thinning, etching, and endpoints be compared by location?
- What are downstream metallization / bonding targets and Cu / liner limits?
Related technical Q&A
- Does measurement separate local Cu reveal height from full-wafer topography?
- Can thinning, etching, and endpoints be compared by location?