TSMC SoIC 3D stacking platform
TSMC · Package architecture and warpage compensation
- Purpose
- TSV-adjacent device review needs the actual 3D stack and supplier design rules.
- Technical approach
- SoIC integrates chips through wafer-level bonding; its SoIC-X wafer-on-wafer architecture uses thin TSVs and tight-pitch bonds.
- Scope of use
- Architecture, die sizes, nodes and compatibility need supplier confirmation for the proposed stack.
- Limitations and open questions
These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitationsPublic descriptions do not provide transferable TSV keep-out distances or stress acceptance values. Conditions differ between stacking schemes.
What to prepareBLNKK suggests preparing die/TSV layouts, adjacent devices, materials/thermal history, selected stack scheme and available design rules.
Confirm with the supplierConfirm PDK/TSV and device-layout rules, compatibility, available analysis data and thermomechanical validation/design approval.
- Public evidence
- TSMC describes design/manufacturing support and distinguishes stacking schemes, including WoW TSVs.
Contact the supplier
Find the company’s contact details and ask about this solution through its official channels.
Related engineering problems
These links use established solution relationships. Continue to engineering conditions and evaluation preparation.
BLNKK organizes information from public sources. A company profile does not imply a documented solution. Applicability still needs confirmation against your samples and engineering conditions.