SOLUTION NAVIGATOREngineering conditions
For “Stress around TSVs and device keep-out design”, add details that may change the assessment order and check the basis and limits of each candidate.
Engineering conditions
Align calibrated measurements of silicon around TSVs, thermal baselines, a model of this stack, and device responses to make relative comparisons of materials and layouts only. Unknowns remain pending confirmation; “assessable” means only that method inputs are complete, not that a diagnosis has been made or qualification passed.
Live assessment
First add location data, measurement calibration, and a pre-fill baseline.
Unconfirmed: Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?; Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?; Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?First add parameters for this stack, thermal history, and corresponding measurements.
Unconfirmed: Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?; Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?; Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?; Does the model use this TSV, liner, silicon orientation, and actual boundary conditions, and is it calibrated against measurements?First add device controls without TSVs, temperature data, and performance criteria.
Unconfirmed: Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?; Do device parameters at the same distance and orientation include controls without TSVs, temperatures, and performance criteria?candidate solutions
The order changes only with conditions you confirm. Public information cannot establish suitability for your actual samples.
After one round of comparisons, choose the next step based on actual observations.
Results only change the order of the next investigation; they do not modify condition answers, prove a root cause, or qualify a solution.
Based on reported conditions and public sources. Ready to assess does not establish sample applicability or root cause. Order does not identify the best solution.
First add location data, measurement calibration, and a pre-fill baseline.
First add parameters for this stack, thermal history, and corresponding measurements.
No result provided. Clarify key conditions before arranging an assessment.
Ye Zhu et al. / author repository · On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias ↗Specific specimens studied in 2016; this does not recommend replacing Cu with CNTs, extrapolate stress magnitudes or keep-out distances, or establish root causes for all Cu TSVs.
NIST authors · Micro-scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-filled Through-Silicon Via ↗Method background from a 2011 W TSV study; W material constants, results, and keep-out distances cannot be transferred to Cu TSVs. Calibration for this stack is required.
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Related solutions
BLNKK measurement study request (provider unconfirmed)
The authors' research supports pairing thermal histories with local observables; a measurement provider able to work on this device must be identified separately.
Basis: Ye Zhu et al. / author repository：On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias；NIST authors：Micro-scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-filled Through-Silicon ViaThe reviewed public information describes a workflow. It has not been linked to a specific product in the BLNKK solution catalogue.
BLNKK device comparison request (provider unconfirmed)
Any route with complete inputs can begin the corresponding evidence comparison; the layout cannot be specified jointly while another evidence segment is missing.
Basis: Ye Zhu et al. / author repository：On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias；NIST authors：Micro-scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-filled Through-Silicon ViaThe reviewed public information describes a workflow. It has not been linked to a specific product in the BLNKK solution catalogue.
BLNKK engineering review request (provider unconfirmed)
Compare relative keep-out, material, and geometry options only when both a calibrated model and actual device-response data are available.
Basis: Ye Zhu et al. / author repository：On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias；NIST authors：Micro-scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-filled Through-Silicon ViaThe reviewed public information describes a workflow. It has not been linked to a specific product in the BLNKK solution catalogue.
Nova
TSV stress changes with geometry and processing; local measurements can be compared with models.
Basis: Nova documents Raman metrology. IBM/Nova’s April 2023 SPIE paper names Elipson and describes measurement-geometry limitations.Nova
TSV stress changes with geometry and processing; local measurements can be compared with models.
Basis: Nova documents Raman metrology. IBM/Nova’s April 2023 SPIE paper names Elipson and describes measurement-geometry limitations.TSMC
TSV-adjacent device review needs the actual 3D stack and supplier design rules.
Basis: TSMC describes design/manufacturing support and distinguishes stacking schemes, including WoW TSVs.Thermo Fisher Scientific
Compare spectra from optically accessible silicon near TSVs to support local strain assessment.
Basis: The November 2024 silicon note names DXR3/DXR3xi; its named strain-imaging example uses DXR3xi.k-Space Associates
TSV stress models need actual thermal-history boundaries.
Basis: The official page describes band-edge/blackbody methods and chamber-specific optical configurations.Bruker
TSV models need independent material-stress evidence.
Basis: The thin-film section names GID, HRXRD and stress/texture analysis, with configurable optics and sample stages.PVA TePla
Regional wafer-stress observations can help compare TSV models and process changes.
Basis: The official product and technology pages describe SIRD transmission measurements and material-specific coefficients.Siemens Digital Industries Software
TSV stress and device-response modeling supports a keepout comparison using actual geometry/material/process data; foundry calibration is necessary for electrical criteria.
Basis: The current product page and 2025 articles describe multiscale analysis and device-level back-annotation. The official FAQ distinguishes coarse package analysis without die detail from feature-level analysis requiring detailed structures and materials.References
Micro-Raman comparisons of Cu and CNT TSV specimens separate pre-existing stress before via filling from the contribution of thermal-expansion mismatch.
Limit: Specific specimens studied in 2016; this does not recommend replacing Cu with CNTs, extrapolate stress magnitudes or keep-out distances, or establish root causes for all Cu TSVs.Research on W TSVs compares Raman measurements with models; silicon anisotropy and process-induced stress must be considered, and peak position does not directly equal a single stress component.
Limit: Method background from a 2011 W TSV study; W material constants, results, and keep-out distances cannot be transferred to Cu TSVs. Calibration for this stack is required.Nova documents Raman metrology. IBM/Nova’s April 2023 SPIE paper names Elipson and describes measurement-geometry limitations.
Limit: Scope and limitations The study’s single-surface geometry cannot separate in-plane/out-of-plane components, and metal coverage blocks the measurement. Spectra do not directly yield a full 3D tensor or safe keep-out distance; detailed maps are not production monitoring throughput. What to prepare BLNKK suggests preparing geometry, crystal orientation, coverage, temperature and process history, with references and scan locations aligned to model coordinates. Confirm with the supplier Confirm optical access, wavelength/polarization, effective depth, conversion/calibration and development-scan or production-sampling strategy. Assess results against device-specific tolerances.TSMC describes design/manufacturing support and distinguishes stacking schemes, including WoW TSVs.
Limit: Scope and limitations Public descriptions do not provide transferable TSV keep-out distances or stress acceptance values. Conditions differ between stacking schemes. What to prepare BLNKK suggests preparing die/TSV layouts, adjacent devices, materials/thermal history, selected stack scheme and available design rules. Confirm with the supplier Confirm PDK/TSV and device-layout rules, compatibility, available analysis data and thermomechanical validation/design approval.The November 2024 silicon note names DXR3/DXR3xi; its named strain-imaging example uses DXR3xi.
Limit: Scope and limitations Silicon examples do not establish DXR3 TSV stress specifications or keep-out acceptance. Arbitrary buried-region coverage is not demonstrated. What to prepare BLNKK suggests preparing orientation, covering layers, locations, thermal histories and low-strain references, with laser conditions checked for heating. Confirm with the supplier Confirm wavelength/access, peak calibration, spatial sampling, stress-conversion models and validation on representative TSV specimens.k-Space documents band-edge sensing and material-dependent calibration.
Limit: Scope and limitations Heavy doping may require another mode, not blanket exclusion. Wafer thermometry does not map packaged junctions or directly predict TSV stress/keep-out. What to prepare BLNKK suggests materials, doping, stacks, windows/optical paths and thermal histories, with calibration and synchronized model-temperature comparisons. Confirm with the supplier Confirm mode, material calibration, access, range/uncertainty and multi-wafer/scanning options.Bruker lists thin-film strain and residual-stress analysis.
Limit: Scope and limitations Sampling and methods depend on configuration and specimen. Lattice strain is not the complete TSV thermal-stress field or a keep-out decision. What to prepare BLNKK suggests phase, orientation, film/process history and references, clarifying material parameters for strain-to-stress conversion. Confirm with the supplier Confirm beam footprint, sampling, geometry/optics, reference and stress-analysis assumptions using representative specimens.The official product and technology pages describe SIRD transmission measurements and material-specific coefficients.
Limit: Scope and limitations The signal represents the measured region and transmission path, not a complete single-TSV stress tensor or device keep-out qualification. What to prepare BLNKK suggests preparing wafer material/thickness, metal and position maps, thermal histories and baseline samples, with the model observable identified. Confirm with the supplier Confirm measurable regions, calibration, spatial resolution and optical-path effects, and how to compare the same observable in measurement and model.The current product page and 2025 articles describe multiscale analysis and device-level back-annotation. The official FAQ distinguishes coarse package analysis without die detail from feature-level analysis requiring detailed structures and materials.
Limit: Scope and limitations Coarse package analysis can proceed without die detail; device-level accuracy needs feature structure/material data. Predictions do not establish universal TSV keep-out distances or electrical-yield qualification. What to prepare BLNKK suggests TSV/device geometry, materials, thermal history, measured stress/device response and foundry acceptance criteria. Confirm with the supplier Confirm software release, input data, back-annotation interfaces and correlation methods, including who validates electrical keep-out criteria.Before assessment