Comparison with local silicon strain or stress measurements
First add location data, measurement calibration, and a pre-fill baseline.
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Compare each solution's purpose, inputs and limits.
For “Stress around TSVs and device keep-out design”, check what each solution can answer before planning validation.
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BLNKK assessment notes
Update engineering conditions →Your next step
Compare purposes and limits now. Confirm key sample conditions before planning validation.
0 solutions selected0 of 5 relevant conditions confirmedNo solutions selected; these notes cover the current engineering problem.
Priority items to confirm · 5
01Surrounding silicon and device locations can be alignedUnconfirmed
Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?
Keep reveal height, liner leakage, and RDL cracks as separate possibilities; nominal TSV diameter cannot localize the response of nearby devices.
Update engineering conditions →02The measurement mapping and probed depth are definedUnconfirmed
Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?
A Raman peak position does not directly equal a single stress component; record measurement temperature, orientation, and surface condition.
Update engineering conditions →03Baseline and thermal-history comparisons are availableUnconfirmed
Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?
Pre-existing stress before via filling and CTE mismatch may coexist; do not extrapolate room-temperature measurements to all operating temperatures.
Update engineering conditions →04The model of this stack can be calibrated against measurementsUnconfirmed
Does the model use this TSV, liner, silicon orientation, and actual boundary conditions, and is it calibrated against measurements?
Material, geometry, residual-stress, and relaxation assumptions must be traceable; W TSV constants and diameter-based rules cannot be transferred to Cu TSVs.
Update engineering conditions →05Device responses and performance criteria are comparableUnconfirmed
Do device parameters at the same distance and orientation include controls without TSVs, temperatures, and performance criteria?
Device orientation and a normal-process baseline are required; a smaller stress contour alone cannot establish an acceptable device keep-out distance.
Update engineering conditions →Relevant assessment paths
Calibrate the model of this stack and make relative comparisons
First add parameters for this stack, thermal history, and corresponding measurements.
Compare device responses and keep-out layouts
First add device controls without TSVs, temperature data, and performance criteria.
Assessment preparation checklist
Discussion preparation based on the relevant engineering conditions; not mandatory supplier requirements or a record of evidence already available.
- Surrounding silicon and device locations can be aligned
- The measurement mapping and probed depth are defined
- Baseline and thermal-history comparisons are available
- The model of this stack can be calibrated against measurements
1 more preparation item
- Device responses and performance criteria are comparable
Check the comparison table above for each solution’s specific inputs and applicability limits.
Questions to discuss
- How do Raman or strain observables correspond to the modeled components?
- Are same-location baselines available for pre-existing stress before filling and for operating temperatures?
- How do this device's orientation, controls without TSVs, and performance criteria guide distance comparisons?
Public references · 9
- Ye Zhu et al. / author repository · On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias ↗
View source notes and limits
Micro-Raman comparisons of Cu and CNT TSV specimens separate pre-existing stress before via filling from the contribution of thermal-expansion mismatch.
Specific specimens studied in 2016; this does not recommend replacing Cu with CNTs, extrapolate stress magnitudes or keep-out distances, or establish root causes for all Cu TSVs.
- NIST authors · Micro-scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-filled Through-Silicon Via ↗
View source notes and limits
Research on W TSVs compares Raman measurements with models; silicon anisotropy and process-induced stress must be considered, and peak position does not directly equal a single stress component.
Method background from a 2011 W TSV study; W material constants, results, and keep-out distances cannot be transferred to Cu TSVs. Calibration for this stack is required.
- Nova · Nova Elipson Raman stress mapping around TSVs ↗
View source notes and limits
Nova documents Raman metrology. IBM/Nova’s April 2023 SPIE paper names Elipson and describes measurement-geometry limitations.
Scope and limitations The study’s single-surface geometry cannot separate in-plane/out-of-plane components, and metal coverage blocks the measurement. Spectra do not directly yield a full 3D tensor or safe keep-out distance; detailed maps are not production monitoring throughput. What to prepare BLNKK suggests preparing geometry, crystal orientation, coverage, temperature and process history, with references and scan locations aligned to model coordinates. Confirm with the supplier Confirm optical access, wavelength/polarization, effective depth, conversion/calibration and development-scan or production-sampling strategy. Assess results against device-specific tolerances.
- TSMC · TSMC SoIC 3D stacking platform ↗
View source notes and limits
TSMC describes design/manufacturing support and distinguishes stacking schemes, including WoW TSVs.
Scope and limitations Public descriptions do not provide transferable TSV keep-out distances or stress acceptance values. Conditions differ between stacking schemes. What to prepare BLNKK suggests preparing die/TSV layouts, adjacent devices, materials/thermal history, selected stack scheme and available design rules. Confirm with the supplier Confirm PDK/TSV and device-layout rules, compatibility, available analysis data and thermomechanical validation/design approval.
- Thermo Fisher Scientific · DXR3 Raman spectra for accessible TSV-adjacent silicon ↗
View source notes and limits
The November 2024 silicon note names DXR3/DXR3xi; its named strain-imaging example uses DXR3xi.
Scope and limitations Silicon examples do not establish DXR3 TSV stress specifications or keep-out acceptance. Arbitrary buried-region coverage is not demonstrated. What to prepare BLNKK suggests preparing orientation, covering layers, locations, thermal histories and low-strain references, with laser conditions checked for heating. Confirm with the supplier Confirm wavelength/access, peak calibration, spatial sampling, stress-conversion models and validation on representative TSV specimens.
- k-Space Associates · kSA BandiT wafer-process temperature comparison ↗
View source notes and limits
k-Space documents band-edge sensing and material-dependent calibration.
Scope and limitations Heavy doping may require another mode, not blanket exclusion. Wafer thermometry does not map packaged junctions or directly predict TSV stress/keep-out. What to prepare BLNKK suggests materials, doping, stacks, windows/optical paths and thermal histories, with calibration and synchronized model-temperature comparisons. Confirm with the supplier Confirm mode, material calibration, access, range/uncertainty and multi-wafer/scanning options.
- Bruker · D8 DISCOVER crystalline-film stress comparison ↗
View source notes and limits
Bruker lists thin-film strain and residual-stress analysis.
Scope and limitations Sampling and methods depend on configuration and specimen. Lattice strain is not the complete TSV thermal-stress field or a keep-out decision. What to prepare BLNKK suggests phase, orientation, film/process history and references, clarifying material parameters for strain-to-stress conversion. Confirm with the supplier Confirm beam footprint, sampling, geometry/optics, reference and stress-analysis assumptions using representative specimens.
- PVA TePla · SIRD optical mapping of regional wafer stress ↗
View source notes and limits
The official product and technology pages describe SIRD transmission measurements and material-specific coefficients.
Scope and limitations The signal represents the measured region and transmission path, not a complete single-TSV stress tensor or device keep-out qualification. What to prepare BLNKK suggests preparing wafer material/thickness, metal and position maps, thermal histories and baseline samples, with the model observable identified. Confirm with the supplier Confirm measurable regions, calibration, spatial resolution and optical-path effects, and how to compare the same observable in measurement and model.
- Siemens Digital Industries Software · Calibre 3DStress multiscale stress and warpage analysis for 3D ICs ↗
View source notes and limits
The current product page and 2025 articles describe multiscale analysis and device-level back-annotation. The official FAQ distinguishes coarse package analysis without die detail from feature-level analysis requiring detailed structures and materials.
Scope and limitations Coarse package analysis can proceed without die detail; device-level accuracy needs feature structure/material data. Predictions do not establish universal TSV keep-out distances or electrical-yield qualification. What to prepare BLNKK suggests TSV/device geometry, materials, thermal history, measured stress/device response and foundry acceptance criteria. Confirm with the supplier Confirm software release, input data, back-annotation interfaces and correlation methods, including who validates electrical keep-out criteria.
Full assessment recordExpand for all conditions, path rules and original assessment notes.
Current assessment and next steps
Based on reported conditions and public sources. Ready to assess does not establish sample applicability or root cause. Order does not identify the best solution.
Known conditions · 0
Key unknowns · 5
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?Keep reveal height, liner leakage, and RDL cracks as separate possibilities; nominal TSV diameter cannot localize the response of nearby devices.
- Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?A Raman peak position does not directly equal a single stress component; record measurement temperature, orientation, and surface condition.
- Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?Pre-existing stress before via filling and CTE mismatch may coexist; do not extrapolate room-temperature measurements to all operating temperatures.
- Does the model use this TSV, liner, silicon orientation, and actual boundary conditions, and is it calibrated against measurements?Material, geometry, residual-stress, and relaxation assumptions must be traceable; W TSV constants and diameter-based rules cannot be transferred to Cu TSVs.
- Do device parameters at the same distance and orientation include controls without TSVs, temperatures, and performance criteria?Device orientation and a normal-process baseline are required; a smaller stress contour alone cannot establish an acceptable device keep-out distance.
Paths to assess
Comparison with local silicon strain or stress measurements
First add location data, measurement calibration, and a pre-fill baseline.
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?
- Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?
- Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?
Conditions that change this path
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?Supports assessment: Surrounding silicon and device locations can be aligned · Unsuitable for now: Only a TSV height or conduction anomaly is available
- Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?Supports assessment: The measurement mapping and probed depth are defined · Unsuitable for now: Only uncalibrated peak positions or a single scalar are available
- Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?Supports assessment: Baseline and thermal-history comparisons are available · Unsuitable for now: Only post-fill room-temperature values are available
Calibrate the model of this stack and make relative comparisons
First add parameters for this stack, thermal history, and corresponding measurements.
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?
- Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?
- Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?
- Does the model use this TSV, liner, silicon orientation, and actual boundary conditions, and is it calibrated against measurements?
Conditions that change this path
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?Supports assessment: Surrounding silicon and device locations can be aligned · Unsuitable for now: Only a TSV height or conduction anomaly is available
- Are local strain or Raman measurements calibrated, with orientation and sampling-depth limitations defined?Supports assessment: The measurement mapping and probed depth are defined · Unsuitable for now: Only uncalibrated peak positions or a single scalar are available
- Are the pre-fill baseline, annealing and operating temperatures, and cooling histories comparable?Supports assessment: Baseline and thermal-history comparisons are available · Unsuitable for now: Only post-fill room-temperature values are available
- Does the model use this TSV, liner, silicon orientation, and actual boundary conditions, and is it calibrated against measurements?Supports assessment: The model of this stack can be calibrated against measurements · Unsuitable for now: Only a generic or uncalibrated model is available
Compare device responses and keep-out layouts
First add device controls without TSVs, temperature data, and performance criteria.
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?
- Do device parameters at the same distance and orientation include controls without TSVs, temperatures, and performance criteria?
Conditions that change this path
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?Supports assessment: Surrounding silicon and device locations can be aligned · Unsuitable for now: Only a TSV height or conduction anomaly is available
- Do device parameters at the same distance and orientation include controls without TSVs, temperatures, and performance criteria?Supports assessment: Device responses and performance criteria are comparable · Unsuitable for now: Only a stress map is available, without device controls
What to do next
No result provided. Clarify key conditions before arranging an assessment.
- Is the anomaly in silicon or active devices around a TSV, with a map of distances, orientations, and device locations?
What to prepare
- Distance / orientation coordinates; Pre- and post-fill baselines and temperature baselines; Measurement depth / calibration
- Location and device orientation; Normal controls without TSVs; Deliverable scope for measurements / performance
- Calibrated model of this stack; Device data by distance, orientation, and temperature; Performance criteria and thermal history
- Optically accessible silicon regions; the official TSV study demonstrates line scans and maps across processes and arrays.
- Architecture, die sizes, nodes and compatibility need supplier confirmation for the proposed stack.
- Evaluate locations yielding usable silicon signals with validated access, references and stress conversion.
- The stated use is wafer/thin-film temperature monitoring during deposition and thermal processing; validate materials, optical access and mode.
- Consider crystalline materials/films with measurable diffraction signals. Confirm representative TSV materials and reference samples.
- Consider optically transmissive wafer regions, with material, thickness, metal coverage and configuration checked.
- For stacked dies, heterogeneous integration and chip-package co-design requiring local stress and assembly-level context. TSV/liner/device geometry and device locations Process-temperature, materials and stress-free references Measured stress/device response and foundry acceptance
Questions to discuss
- How do Raman or strain observables correspond to the modeled components?
- Are same-location baselines available for pre-existing stress before filling and for operating temperatures?
- How do this device's orientation, controls without TSVs, and performance criteria guide distance comparisons?
Public references
Ye Zhu et al. / author repository · On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias ↗Specific specimens studied in 2016; this does not recommend replacing Cu with CNTs, extrapolate stress magnitudes or keep-out distances, or establish root causes for all Cu TSVs.
NIST authors · Micro-scale Measurement and Modeling of Stress in Silicon Surrounding a Tungsten-filled Through-Silicon Via ↗Method background from a 2011 W TSV study; W material constants, results, and keep-out distances cannot be transferred to Cu TSVs. Calibration for this stack is required.
Nova · Nova Elipson Raman stress mapping around TSVs ↗Scope and limitations The study’s single-surface geometry cannot separate in-plane/out-of-plane components, and metal coverage blocks the measurement. Spectra do not directly yield a full 3D tensor or safe keep-out distance; detailed maps are not production monitoring throughput. What to prepare BLNKK suggests preparing geometry, crystal orientation, coverage, temperature and process history, with references and scan locations aligned to model coordinates. Confirm with the supplier Confirm optical access, wavelength/polarization, effective depth, conversion/calibration and development-scan or production-sampling strategy. Assess results against device-specific tolerances.
TSMC · TSMC SoIC 3D stacking platform ↗Scope and limitations Public descriptions do not provide transferable TSV keep-out distances or stress acceptance values. Conditions differ between stacking schemes. What to prepare BLNKK suggests preparing die/TSV layouts, adjacent devices, materials/thermal history, selected stack scheme and available design rules. Confirm with the supplier Confirm PDK/TSV and device-layout rules, compatibility, available analysis data and thermomechanical validation/design approval.
Thermo Fisher Scientific · DXR3 Raman spectra for accessible TSV-adjacent silicon ↗Scope and limitations Silicon examples do not establish DXR3 TSV stress specifications or keep-out acceptance. Arbitrary buried-region coverage is not demonstrated. What to prepare BLNKK suggests preparing orientation, covering layers, locations, thermal histories and low-strain references, with laser conditions checked for heating. Confirm with the supplier Confirm wavelength/access, peak calibration, spatial sampling, stress-conversion models and validation on representative TSV specimens.
k-Space Associates · kSA BandiT wafer-process temperature comparison ↗Scope and limitations Heavy doping may require another mode, not blanket exclusion. Wafer thermometry does not map packaged junctions or directly predict TSV stress/keep-out. What to prepare BLNKK suggests materials, doping, stacks, windows/optical paths and thermal histories, with calibration and synchronized model-temperature comparisons. Confirm with the supplier Confirm mode, material calibration, access, range/uncertainty and multi-wafer/scanning options.
Bruker · D8 DISCOVER crystalline-film stress comparison ↗Scope and limitations Sampling and methods depend on configuration and specimen. Lattice strain is not the complete TSV thermal-stress field or a keep-out decision. What to prepare BLNKK suggests phase, orientation, film/process history and references, clarifying material parameters for strain-to-stress conversion. Confirm with the supplier Confirm beam footprint, sampling, geometry/optics, reference and stress-analysis assumptions using representative specimens.
PVA TePla · SIRD optical mapping of regional wafer stress ↗Scope and limitations The signal represents the measured region and transmission path, not a complete single-TSV stress tensor or device keep-out qualification. What to prepare BLNKK suggests preparing wafer material/thickness, metal and position maps, thermal histories and baseline samples, with the model observable identified. Confirm with the supplier Confirm measurable regions, calibration, spatial resolution and optical-path effects, and how to compare the same observable in measurement and model.
Siemens Digital Industries Software · Calibre 3DStress multiscale stress and warpage analysis for 3D ICs ↗Scope and limitations Coarse package analysis can proceed without die detail; device-level accuracy needs feature structure/material data. Predictions do not establish universal TSV keep-out distances or electrical-yield qualification. What to prepare BLNKK suggests TSV/device geometry, materials, thermal history, measured stress/device response and foundry acceptance criteria. Confirm with the supplier Confirm software release, input data, back-annotation interfaces and correlation methods, including who validates electrical keep-out criteria.