Foveros Direct 3D chiplet integration with Cu-to-Cu hybrid bonding

Intel Foundry · Package architecture and warpage compensation

Purpose: AI/HPC multi-die systems need dense vertical links alongside power, cooling, stack-up and bond-reliability assessment.
Technical approach: Cu-to-Cu hybrid bonding replaces solder microbumps for chiplets stacked on an active base die, with EMIB combination options.
Scope of use: For client, data-center and AI/HPC 3D integration. The dedicated brief limits availability to Intel Foundry process nodes; confirm access/supply.
Limitations and open questions: These evaluation considerations are compiled by BLNKK from public information. They are not supplier guarantees or a mandatory submission checklist.
Scope and limitations
A co-designed foundry platform, not a standalone part. Node/design restrictions apply; customer warpage, thermal resistance and bond yield are not guaranteed by positioning claims.
What to prepare
BLNKK suggests preparing dies/nodes, interconnect/power, thickness/stack-up, cooling, interfaces and test/reliability targets.
Confirm with the supplier
Confirm nodes/rules, access/schedule, qualified stacks/bonding, thermomechanical data, test strategy and EMIB combinations.
Public evidence: Intel’s packaging page and November 2025 Direct 3D technology brief describe vertical hybrid bonding and EMIB 3.5D integration. The dedicated brief is the evidence for this solution; Foveros 2.5D literature is not substituted for it.

Supporting references

Find the company’s contact details and ask about this solution through its official channels.