Local review · not published
7980 wafer 2D/3D metrology
Chroma ATE · Metrology and inspection
Research candidate · suitability unconfirmed
Official public page; sample suitability remains unconfirmed.
Research checked: 2026-10-17- Purpose
- Compare exposed TSV, bump and pre-bond surface geometry.
- Technical approach
- BLiS optical profilometry with image stitching.
- Scope of use
- Supplier-listed wafer formats and optically accessible surfaces; validate your sample.
- Limitations and open questions
- Resolution is not accuracy. Validate reflectivity, occlusion, tilt correction and repeatability. Surface data cannot establish buried voids, chemistry or bond yield.
- Public evidence
- Official global and US pages list TSV, bump/step height and roughness applications.
Supporting references
Contact the supplier
Find the company’s contact details and ask about this solution through its official channels.
Potential uses by engineering problem
TSV reveal height and backside coplanarity
Surface height/step measurements can support exposed-TSV topography comparison.
Confirm Cu/Si optical response, datum and repeatability; data alone do not select etch or CMP conditions.
View engineering problem →Microbump height variation and coplanarity
Supplier-listed bump-height metrology supports pre-bond array height comparison.
Separate tilt, wafer bow and bump variation; qualify the actual geometry and material.
View engineering problem →Pre-bond surface readiness and release for hybrid bonding
Surface profile/roughness data may support pre-bond geometry checks; this is an editorial inference.
No product-specific Cu-recess or roughness release limit is established. Chemistry, activation and bondability require other evidence.
View engineering problem →BLNKK organizes information from public sources. A company profile does not imply a documented solution. Applicability still needs confirmation against your samples and engineering conditions.