Neptune CT and Voyager analysis
Potential engineering use: [3D void topology and thermal risk] Quantify 3D location and shape of existing solder/adhesive voids. [Flip-chip solder bridging] Compare placement/reflow conditions with bridge locations.
Research candidate · suitability unconfirmed
Official public page; sample suitability remains unconfirmed.
Research checked: 2026-10-15Potential uses by engineering problem
Why can the same void percentage imply different thermal risks?
Quantify 3D location and shape of existing solder/adhesive voids.
Pair CT with thermal tests; sample-dependent resolution cannot yield a universal acceptance percentage.
View engineering problem →Solder bridging after flip-chip reflow
Compare placement/reflow conditions with bridge locations.
Verify solder volume, pitch and electrical results; board-level BGA results are not direct flip-chip evidence.
View engineering problem →