Intravia morphology and representative sampling
First obtain pre-assembly intravia locations and batch maps.
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Compare each solution's purpose, inputs and limits.
For “Internal voids in substrate microvia copper fill”, check what each solution can answer before planning validation.
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BLNKK assessment notes
Update engineering conditions →Your next step
Compare purposes and limits now. Confirm key sample conditions before planning validation.
0 solutions selected0 of 4 relevant conditions confirmedNo solutions selected; these notes cover the current engineering problem.
Priority items to confirm · 4
01Pre-assembly copper-fill body anomaly localizedUnconfirmed
Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?
Separate incomplete intravia fill, dimples, and Cu / Cu interface cracks. Do not label every dark X-ray region a void.
Update engineering conditions →02Via geometry / batch / location sampling is comparableUnconfirmed
Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?
Preserve via diameter / depth and sampling direction. A single cross-section cannot establish the void fraction across an entire batch.
Update engineering conditions →03Via-formation / pretreatment histories are comparableUnconfirmed
Are drilling, desmear, wetting / electroless copper, and waiting histories before copper filling traceable?
Observe via-wall and bottom metallization quality. A public process sequence does not establish that a particular pretreatment caused this via's voids.
Update engineering conditions →04Electroplating / bath and solution-flow records are comparableUnconfirmed
Are current, additives / CVS, solution flow, and bath / equipment conditions comparable for the same via geometry?
Record actual equipment and chemistry. Do not directly apply public SAP3 values or infer additives from void shapes.
Update engineering conditions →Relevant assessment paths
Via formation / pretreatment / metallization comparisons
First obtain via geometry, metallization evidence, and waiting / treatment traces.
Copper-fill electroplating and location-distribution comparisons
First obtain shared via geometry and electroplating / solution-flow traces.
Assessment preparation checklist
Discussion preparation based on the relevant engineering conditions; not mandatory supplier requirements or a record of evidence already available.
- Pre-assembly copper-fill body anomaly localized
- Via geometry / batch / location sampling is comparable
- Via-formation / pretreatment histories are comparable
- Electroplating / bath and solution-flow records are comparable
Check the comparison table above for each solution’s specific inputs and applicability limits.
Questions to discuss
- Is the void in the copper-fill body or at a Cu / Cu interface after thermal loading?
- Are via geometry, panel locations, and normal / abnormal sampling representative?
- How can comparable histories of pretreatment, waiting, CVS, current, and solution flow be preserved?
Public references · 9
- ASE · Failure Analysis Lab ↗
View source notes and limits
Lists capabilities for electrical failure localization, nondestructive X-ray inspection, and targeted cross-section / FIB analysis.
The service list does not guarantee detection rates at every RDL or microvia scale; sampling, structures, and destructive risks require confirmation.
- MKS / Atotech · InPro SAP3 ↗
View source notes and limits
The IC-substrate blind-microvia copper-fill electrolyte is used in VCP. Additives can be controlled using CVS, with claimed via-fill and thickness uniformity.
Product capabilities apply to the specified system. They do not establish the cause of this batch's voids; do not directly adopt current density, via dimensions, or dimple values.
- MKS / Atotech · Optimize the interconnect ↗
View source notes and limits
The source connects laser drilling, surface treatment, desmear, electroless copper, and electroplating into a microvia-interconnect process.
An integrated-capability description; it supplies no causal evidence for these intravia voids or pretreatment recipe ready for direct use.
- MKS’ Atotech · InPro MVF blind-microvia copper filling ↗
View source notes and limits
The MVF/MVF2 page describes process configuration and filling examples; a separate portfolio explains the broader InPro family.
Scope and limitations Family-level pulse plating and IC-substrate applications do not establish MVF suitability. Examples and reliability statements do not guarantee void-free filling or qualification for every geometry. What to prepare BLNKK suggests via dimensions, materials/seed layers, existing plating conditions, cross-section defects and surface-copper targets. Confirm with the supplier Confirm MVF/MVF2 selection, geometry-specific process windows, agitation/replenishment, acceptance criteria and reliability-test conditions.
- Rigaku · nano3DX 3D X-ray sampling of substrate copper-fill voids ↗
View source notes and limits
Rigaku describes the imaging method; its 2019 journal article demonstrates internal electronic-component and PCB imaging.
Scope and limitations Metal thickness and settings affect penetration/contrast. Voxel size is not defect-detection size; images do not establish electrical continuity or chemical identity. What to prepare BLNKK suggests preparing stack-up, copper thickness, specimen dimensions, suspected void locations/sizes and representative samples for section correlation. Confirm with the supplier Confirm targets, field of view, acquisition/reconstruction, defect recognition and repeatability; discuss correlation with cross-sections.
- MacDermid Alpha Electronics Solutions · MacDermid Alpha Systek VTP 100 via-fill/RDL plating ↗
View source notes and limits
The named FAQ describes bottom-up filling and uniform line profiles, without geometry-specific void acceptance limits.
Scope and limitations It neither inspects nor repairs existing voids, and does not guarantee void-free filling. Other PLP products’ rates, low-Kirkendall-void or barrier features do not transfer. What to prepare BLNKK suggests documenting geometry/aspect ratio, density, seed continuity, pretreatment, bath and current, with section or 3D-fill comparisons. Confirm with the supplier Confirm usable geometry, seed/dielectric compatibility, operating window and bath control, and agree fill, profile and reliability validation.
- LPKF Laser & Electronics SE · NEXAR LIDE glass via and microstructure fabrication ↗
View source notes and limits
Official pages describe the NEXAR LIDE 5000 M/S/P variants and the two-step technology.
Scope and limitations Glass feature formation does not ensure void-free metal filling or establish suitability for silicon TSV processing. What to prepare BLNKK suggests preparing glass composition and thickness, feature drawings and tolerances, substrate format and the downstream metallization flow. Confirm with the supplier Confirm the current configuration, supported glass and etching integration, and how sample geometry, surface quality and filling compatibility will be evaluated.
- ULVAC, Inc. · SMV-500F interposer Ti/Cu seed sputtering ↗
View source notes and limits
The product page documents seed sputtering and cooling, without project-specific internal coverage evidence.
Scope and limitations PCB-interposer use does not establish continuous coverage in high-aspect-ratio TSVs or compliance with every substrate's thermal limit. What to prepare BLNKK suggests preparing geometry, target thickness, surface and thermal-budget details, then correlating cross-sections and electrical measurements with fill results. Confirm with the supplier Confirm substrate/chamber configuration, Ti/Cu stack and cooling, plus geometry-specific coverage, continuity and adhesion validation.
- Allied High Tech Products, Inc. · MultiPrep targeted cross-section polishing ↗
View source notes and limits
The official page documents orientation/removal control and separately sold fixtures and platens.
Scope and limitations A section may miss the target void and does not alone establish an original fill defect. BLNKK advises checking smear, pull-out and section-offset artifacts. What to prepare BLNKK suggests preparing locations/imaging, layer details, section direction and controls, with cutting/mounting/polishing and removal history retained. Confirm with the supplier Confirm fixtures, platens, abrasives, targeting/stopping and microscopy or repeat-section checks for location and preparation quality.
Full assessment recordExpand for all conditions, path rules and original assessment notes.
Current assessment and next steps
Based on reported conditions and public sources. Ready to assess does not establish sample applicability or root cause. Order does not identify the best solution.
Known conditions · 0
Key unknowns · 4
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?Separate incomplete intravia fill, dimples, and Cu / Cu interface cracks. Do not label every dark X-ray region a void.
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?Preserve via diameter / depth and sampling direction. A single cross-section cannot establish the void fraction across an entire batch.
- Are drilling, desmear, wetting / electroless copper, and waiting histories before copper filling traceable?Observe via-wall and bottom metallization quality. A public process sequence does not establish that a particular pretreatment caused this via's voids.
- Are current, additives / CVS, solution flow, and bath / equipment conditions comparable for the same via geometry?Record actual equipment and chemistry. Do not directly apply public SAP3 values or infer additives from void shapes.
Paths to assess
Intravia morphology and representative sampling
First obtain pre-assembly intravia locations and batch maps.
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?
Conditions that change this path
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?Supports assessment: Pre-assembly copper-fill body anomaly localized · Unsuitable for now: Only later interface cracks or vias outside the substrate
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?Supports assessment: Via geometry / batch / location sampling is comparable · Unsuitable for now: Only isolated cross-sections
Via formation / pretreatment / metallization comparisons
First obtain via geometry, metallization evidence, and waiting / treatment traces.
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?
- Are drilling, desmear, wetting / electroless copper, and waiting histories before copper filling traceable?
Conditions that change this path
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?Supports assessment: Pre-assembly copper-fill body anomaly localized · Unsuitable for now: Only later interface cracks or vias outside the substrate
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?Supports assessment: Via geometry / batch / location sampling is comparable · Unsuitable for now: Only isolated cross-sections
- Are drilling, desmear, wetting / electroless copper, and waiting histories before copper filling traceable?Supports assessment: Via-formation / pretreatment histories are comparable · Unsuitable for now: Insufficient pretreatment / metallization histories
Copper-fill electroplating and location-distribution comparisons
First obtain shared via geometry and electroplating / solution-flow traces.
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?
- Are current, additives / CVS, solution flow, and bath / equipment conditions comparable for the same via geometry?
Conditions that change this path
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?Supports assessment: Pre-assembly copper-fill body anomaly localized · Unsuitable for now: Only later interface cracks or vias outside the substrate
- Can via geometry, panel location, batch, and normal / abnormal sampling be correlated?Supports assessment: Via geometry / batch / location sampling is comparable · Unsuitable for now: Only isolated cross-sections
- Are current, additives / CVS, solution flow, and bath / equipment conditions comparable for the same via geometry?Supports assessment: Electroplating / bath and solution-flow records are comparable · Unsuitable for now: Shared electroplating histories are missing
What to do next
No result provided. Clarify key conditions before arranging an assessment.
- Have pre-assembly voids / seams been localized to the copper-fill body in organic-substrate microvias?
What to prepare
- Pre-assembly via-geometry / location maps; Normal / abnormal samples; Targeted cross-sections and non-destructive data
- Shared via geometry and void distributions; Actual VCP / bath and CVS traces; Current / solution flow and normal samples
- Via-formation / metallization samples and histories; Electroplating / solution-flow traces for the same via geometry; Representative normal / abnormal locations
- Listed uses include HDI/flex PCBs, with or without conformal through-hole plating. IC substrates and particular via geometries require confirmation.
- Substrates or coupons need adequate penetration/contrast and suitable dimensions and rotation clearance.
- A via-fill/RDL process candidate, subject to actual geometry and material compatibility.
- Consider it for glass-core substrates, interposers and glass microstructures, with material and equipment configurations assessed for the project.
- ULVAC explicitly names PCB interposers; geometry and material suitability require confirmation.
- Consider destructive substrate/package preparation with material-specific fixtures and abrasives.
Questions to discuss
- Is the void in the copper-fill body or at a Cu / Cu interface after thermal loading?
- Are via geometry, panel locations, and normal / abnormal sampling representative?
- How can comparable histories of pretreatment, waiting, CVS, current, and solution flow be preserved?
Public references
ASE · Failure Analysis Lab ↗The service list does not guarantee detection rates at every RDL or microvia scale; sampling, structures, and destructive risks require confirmation.
MKS / Atotech · InPro SAP3 ↗Product capabilities apply to the specified system. They do not establish the cause of this batch's voids; do not directly adopt current density, via dimensions, or dimple values.
MKS / Atotech · Optimize the interconnect ↗An integrated-capability description; it supplies no causal evidence for these intravia voids or pretreatment recipe ready for direct use.
MKS’ Atotech · InPro MVF blind-microvia copper filling ↗Scope and limitations Family-level pulse plating and IC-substrate applications do not establish MVF suitability. Examples and reliability statements do not guarantee void-free filling or qualification for every geometry. What to prepare BLNKK suggests via dimensions, materials/seed layers, existing plating conditions, cross-section defects and surface-copper targets. Confirm with the supplier Confirm MVF/MVF2 selection, geometry-specific process windows, agitation/replenishment, acceptance criteria and reliability-test conditions.
Rigaku · nano3DX 3D X-ray sampling of substrate copper-fill voids ↗Scope and limitations Metal thickness and settings affect penetration/contrast. Voxel size is not defect-detection size; images do not establish electrical continuity or chemical identity. What to prepare BLNKK suggests preparing stack-up, copper thickness, specimen dimensions, suspected void locations/sizes and representative samples for section correlation. Confirm with the supplier Confirm targets, field of view, acquisition/reconstruction, defect recognition and repeatability; discuss correlation with cross-sections.
MacDermid Alpha Electronics Solutions · MacDermid Alpha Systek VTP 100 via-fill/RDL plating ↗Scope and limitations It neither inspects nor repairs existing voids, and does not guarantee void-free filling. Other PLP products’ rates, low-Kirkendall-void or barrier features do not transfer. What to prepare BLNKK suggests documenting geometry/aspect ratio, density, seed continuity, pretreatment, bath and current, with section or 3D-fill comparisons. Confirm with the supplier Confirm usable geometry, seed/dielectric compatibility, operating window and bath control, and agree fill, profile and reliability validation.
LPKF Laser & Electronics SE · NEXAR LIDE glass via and microstructure fabrication ↗Scope and limitations Glass feature formation does not ensure void-free metal filling or establish suitability for silicon TSV processing. What to prepare BLNKK suggests preparing glass composition and thickness, feature drawings and tolerances, substrate format and the downstream metallization flow. Confirm with the supplier Confirm the current configuration, supported glass and etching integration, and how sample geometry, surface quality and filling compatibility will be evaluated.
ULVAC, Inc. · SMV-500F interposer Ti/Cu seed sputtering ↗Scope and limitations PCB-interposer use does not establish continuous coverage in high-aspect-ratio TSVs or compliance with every substrate's thermal limit. What to prepare BLNKK suggests preparing geometry, target thickness, surface and thermal-budget details, then correlating cross-sections and electrical measurements with fill results. Confirm with the supplier Confirm substrate/chamber configuration, Ti/Cu stack and cooling, plus geometry-specific coverage, continuity and adhesion validation.
Allied High Tech Products, Inc. · MultiPrep targeted cross-section polishing ↗Scope and limitations A section may miss the target void and does not alone establish an original fill defect. BLNKK advises checking smear, pull-out and section-offset artifacts. What to prepare BLNKK suggests preparing locations/imaging, layer details, section direction and controls, with cutting/mounting/polishing and removal history retained. Confirm with the supplier Confirm fixtures, platens, abrasives, targeting/stopping and microscopy or repeat-section checks for location and preparation quality.