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Engineering problems4
TSV / through-silicon via and insulation
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14
TSV reveal height and backside coplanarity
Separate relative Cu reveal height from full-wafer topography, then use staged thinning / reveal maps to define upstream, etch, or pre-bond surface requirements.
Revealed TSV Cu and backside bonding surfaces after thinning · Backside reveal through pre-metallization / bonding
Use depth-resolved copper distributions in deep silicon vias to separate seed/wetting comparisons from bath/flow comparisons. Retain later reveal and bond-interface issues separately.
Electroplated copper inside TSVs in silicon · Deep-via copper filling and before/after subsequent CMP
Align calibrated measurements of silicon around TSVs, thermal baselines, a model of this stack, and device responses to make relative comparisons of materials and layouts only.
Silicon around TSVs and nearby active devices · Thermal annealing, operation, and layout verification
First confirm the TSV-to-silicon bulk topology, aggregate geometry, and low-current background, then compare liner depth and process contamination using controls that have not undergone breakdown.
Insulating liner between TSV copper and silicon · Via formation, after liner deposition or copper filling, and bias verification
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