Temporary bonding and low-stress debonding for thin wafers
Thin and reconstituted wafers need mechanical support during thinning, backside processing and transfer to manage warpage and breakage risk.
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View contact information ↓Applications: Thin wafers, FoWLP and 3D integration · 3D IC, memory stacking, BSI CIS and hybrid bonding · chiplet / 3D IC / heterogeneous integration · Die-to-wafer alignment · Fan-out redistribution lithography
Thin and reconstituted wafers need mechanical support during thinning, backside processing and transfer to manage warpage and breakage risk.
3D IC and memory stacking require controlled wafer cleaning, activation and alignment to establish suitable interfaces and interconnects for fusion or hybrid bonding.
Particles, surface chemistry and the interval between cleaning and bonding can affect die-to-wafer hybrid bonding. Die preparation needs to be assessed alongside the downstream placement flow.
Map post-bond die-to-wafer overlay errors to compare placement distributions and process feedback.
Fan-out die movement requires matching subsequent RDL exposure patterns to actual positions and verifying alignment.
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